糖心Vlog

演讲者：汪波 博士（ 法国利摩日大学   高频器件与电路专业博士）

时  间：2011年11月23日  16:10-16:50pm

地  点：北大深研院C202教室

题  目：Design and modeling for RF PLL circuits: challenge and strategy

摘要:

Nowadays, the RF front end of new communications systems is implemented with very large integration (RF-SoC), involving all functions (amplification, filtering, mixing and frequency synthesizer) into one chip. Through this integration, today’s RF front end design requires rigorous simulation/optimization/verification of entire communication system.

Among all the building blocks of communication system, PLL circuit (phase locked loop) is of our special interest for its wide applications in clock data recovery, RFID, Wi-Fi, etc. On one hand, PLL serves as heart of the communication system; on the other hand, the PLL circuit, containing both aspects of digital signal processing and analog RF signals (VCO), becomes the bottle-neck of the whole system design.

This talk deals with the design and verification methodology of the PLL circuits, as well as the modeling and simulation techniques for the critical PLL characteristics (such as phase noise, settling time). The conventional simulation methods in RF EDA tools are precise but spend such a long time (days, weeks). As a result, some important characteristics cannot even be verified before tape-out because of lack of appropriate building block model.

In this context, accurate and quick design/verification methodology should be developed. This requires creating novel building block models on various abstraction levels (functional or mixed functional/transistor-level). This also needs developing appropriate simulation strategy such as reduced-order modeling of black box, mixed analog-digital co-simulation, etc. These new models, realized in standard behavioral language (Verilog-A), allows for creation of building block libraries within the current EDA tools and IP reuse